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130 Patents of invention 

 

patent application number

title of invention

1

200310120546.2

X-ray lithography Alignment marks

2

 200310122345.6

Novel Structure Schottky millimeter mixer diode

3

200410002011.X

An analysis method of Average performance of asynchronous data channel

4

200410001433.5

Fabrication of air bridge by means of composite glue electroplating

5

200410002012.4

Asynchronous Adding selected comparator 

6

200410039695.0 

A method of forming plating layer on semiconductor substrate 

7

200510005742.4

A method of flexible controlling lithography development time with a unique layout design 

8

200510006189.6

A method to prevent from flawing in ZEP520 resist 

9

200510008008.3  

A method of exposing sub-50nm pattern with use of chemical amplified negative resist 

10

200510008009.8  

A method of X-ray mask preparation by using single small and large current mixing exposure

11

200410035089.1

A method of dielectric partial thickening to increase the integrated electrical inductance of silicon substrate

12

200410035088.7

A method of silicide self-alignment used for FET transistor of RF transverse diffusion 

13

200410047532.7

 A method of making mask for polysilicon gate etching with thickness of line at nanometer scale

14

200410047533.1

An method for polysilicon gate etching with thickness of line at  15-50 nanometer scale 

15

200410045979.0 

The integrated structure of Bulk Silicon RFIC and its fabrication

16

200410058033.8

An ohmic contact system suitable for aluminum/titan/aluminum/titan/Platinum/gold in gallium nitride device

17

 200410058034.2

A ohmic contact system suitable for aluminum/titan/aluminum/Platinum/gold in gallium nitride device

18

200410058035.7

An ohmic contact system suitable for aluminum/titan/aluminum/Ni/gold in gallium nitride device.

19

200410058036.1

 An ohmic contact system suitable for titan/aluminum/titan/Platinum/gold in gallium nitride device

20

200410058037.6

An ohmic contact system suitable for aluminum/titan/aluminum/titan/gold in gallium nitride device 

21

200410074678.0  

A high-speed simulator method based on static random access memory and its preparation method

22

200410074677.6  

A method to increase hole mobility of PMOS FET

23

200410080409.5

 A silicide technology suitable for fabrication of Nanometer devices 

24

200410081007.7

 A Frequency Divider suitable for random programming and its fabrication method

25

200410083804.9

A fast integrated design method based on static random access memory 

26

200410088513.9

Structure and preparation method for fish raphe type FET

27

200410095295.1

A dry etching method for thick aluminum with high precision 

28

200410009933.3 

A method to fabricate deep nanometer T-gate by using single nano- impression 

29

200410009932.9  

A system structure of integrated phase locked loop 

30

200410009984.6 

 A method to improve capacitance characteristic of metal-dielectric-metal structure 

31

200410098992.2  

A method to fabricate T-type gate by using combination of nanometer impression and optical lithography 

32

200410098991.8.  

A capacitor fabricated with pure digital process 

33

200410101872.3  

A fabrication process for high aspect ratio deep sub-micron, nanometer metal structures with 3 layers

34

200410101873.8 

 A fabrication process based on self-supported film for high aspect ratio deep sub-micron, nanometer metal structures with 3 layers

35

200410101871.9  

A encapsulation annealing method applied to GaN-based materials 

36

200510052691.0  

Method of keeping time’s fast convergence in SLSI

37

200510063879.5

 A microstrip array with high gain and wide angle Field Pattern

38

200510062484.3

A method of preparation of electrical tunable optical filter chip in micro -electric machinery system 

39

200510062485.8

A protection method for aluminum reflecting electrode of silicon-based liquid crystal 

40

200510011506.3

A method of preparation of gate substitution 

41

200510011738.9

A method for fabrication of T-type gate with high electron mobility in transistor circuit 

42

200510056279.6

A preparation method for exposing aligning marks by means of combination and matching of electron beam and optical methods

43

200510056280.9  

A method to fabricate 100nm pattern by using technology of full transparent non -Cr phase shift mask 

44

200510071093.8 

A metal alloy system suitable for ohmic contacts in high speed gallium arsenide based devices 

45

200510011845.1  

A  high voltage MOS double grids preparation process compatible with standard MOS process

46

 200510011893.0  

A Ga-based depletion mode PHEMT material

47

200510011988.2 

A  method to fabricate FPA of single layer and bi-material micro -cantilever beam with heat Isolation 

48

200510011989.7

A method  for fabrication of salient point and sacrificed layer on silicon substrate 

49

200510011987.8 

 Micro-probe Line Array device 

50

200510011990.  

A preparation method for organic molecule crossbar array 

51

200510012172.1  

A area array device of new micro-probe 

52

200510012171.7 

 A method of preparation for Organic crossbar array by using silicon oxide filling and etching back processes 

53

200510012238.7

A fabrication method for Heat shearing stress sensor device by using vacuum bonding process 

54

200510012239.1  

A fabrication method for Heat shear stress sensor device by using New sacrificial layer 

55

200510085294.3  

A method to prepare Nanometer electrode based on silicon nitride engraving process 

56

200510012264.x  

FPA of photo -mechanical and double-layer Infrared imaging without cooling 

57

200510088979.3  

A   material Structure of InGaP Enhancement/Depletion-Mode strained high-electron-mobility transistors 

58

200510088980.6  

Structure of GaAs-based Enhancement/Depletion-Mode strained high electron mobility transistor material 

59

200510090179.5  

A fabrication method used for improving the performances of uncooled Infrared FPA device 

60

200510093369.2  

A gate fabrication process for GaAs-based Enhancement/Depletion-Mode PHEMT transistor 

61

200510086316.8  

A Variable Length Decoder based on keywords and its method

62

200510103016.6  

A asynchronous fast Fourier transform processor

63

200510103017.0  

A asynchronous butterfly computing unit circuit

64

200510086488.5  

A method of preparation of  dielectric used for ultrathin silicon nitride/silicon dioxide stack gates 

65

200510109338.1  

A method to prepare organic Cross array by using Self-Assembly technique 

66

200510086643.3  

A Synchronization method of program streams between  programmable universal multicore processors on a chip 

67

200510086971.3  

A method of preparation of Vibration flow actuator in micro -electric machinery System

68

200510123888.9  

A preparation method of metal anode and cathode Isolation posts for silicon-based organic light emitting micro-display

69

200510126232.2  

A method of preparation of SAW device by using mix-match between Nanometer impression and photo lithography

70

200510130437.8  

A method of preparation of Nanometer impression mold with ultraviolet hardening

71

200510130438.2  

A method to fabricate metal nanometer electrode by using positive photoresist

72

200510127446.1  

A method based on fabrication of salient point on silicon substrate and releasing sacrifice layer

73

200510126492.X  

A method of preparation of nanometer impression mold by using multi-sidewall technology

74

200510130692.2   

A structure of two dimensional square lattice lay-out of multiprocessor chip

75

200510130693.7

A method of designing Power Grids based on power distribution

76

200510130772.8  

A real time  bit-true simulation development system and its method

77

200510130758.8  

A non-planar channel organic FET

78

200610002666.6  

Design and fabrication process for a optical switch

79

200610001709.9  

A  RF signal integrated ESD protection circuit  by using Inductance

80

200610001710.1  

A RF signal integrated ESD protection circuit in CMOS process

81

200610003067.6  

A fabrication method for high resolution, self-supported, full-engraved transmission grating

82

200610003068.0  

A method to fabricate phase shift mask with sidewall chromium Attenuation used in 193nm  optical lithography

83

200610003531.1  

A method to fabricate nanometer electrode with negative photoresist 

84

200610003070.8  

A method of forming via hole on InP substrate and semiconductor optoelectronic devices

85

200610003066.1  

The method improvement to fabricate  T-type emitter metal pattern of heterojunction bipolar transistor 

86

200610003069.5  

A packaging structure and method of high speed semiconductor light emission module 

87

200610003586.2  

A method of preparation for SAW device

88

200610066309.6  

A  method to protect digital contents based on binding to hardware components

89

200610066888.4  

A fabrication method for non -cooling Infrared FPA based on silicon substrate non -sacrifice layer 

90

200610066308.1  

A content protection method based on content segmentation 

91

200610011728.X  

A high sensitivity tracking technology of GPS signal carrier

92

200610011729.4  

A  tracking technology of high sensitivity GPS receiver baseband with variable gain

93

200610076012.8  

A method of GPS signal acquisition with FFT 

94

200610076010.9  

A auto-tuning circuit on chip with integrated low noise active filter 

95

200610074546.7  

A forcing block decision feedback method for TD-SCDMA receiving signal demodulation

96

200610074548.6  

A TD SCDMA receiving signal demodulation method with use of Block -FFT 

97

200610076011.3  

A frequency offset estimation method of communication system with Orthogonal Frequency Division Multiplexing

98

200610078217.X  

A PI Design solution based on synergia of IC packaging and PCB 

99

200610078216.5  

A  jitter clock recovery circuit with binary phase shift keying modulation

100

200710099548.6  

A dual mode Frequency Divider 

101

200610012048.X  

A fixed-base FFT processor with low number of memory and its method

102

200610012046.0  

A method of designing reset circuit for system on chip

103

200610012051.1  

A method of  preparation for organic molecule Cross Line array  in nano scale

104

200610012052.6  

A method to fabricate anisotropic organic FET with combination of using impression technology

105

200610012053.0 

 A method for fabrication of mold-based anisotropic organic FET

106

200610083332.6  

A method to fabricate anisotropic organic FET by using hot-pressing 

107

200610012054.5  

A digital offset voltage automatic calibration circuit of the op amp and its method

108

200610012050.7  

A self-start  low voltage current mirror

109

200610012047.5  

A universal IP testing method  in compliance with IEEE  1149.1 protocol

110

200610012049.4  

A mixed-base FFT processor with low number of memory and its method 

111

200610012129.X  

A method of preparation of nano-scale Columb island structure

112

200610083996.2  

A method of designing RF Single electron transistor displacement sensor

113

200610083997.7  

A method to connect gate bulk  to SOI dynamic threshold transistor with reverse bias Schottky junction 

114

200610012246.6  

A  silicon-based  single electron transistor with planar side-edge gate and its fabrication method

115

200610083998.1  

A high mobility and anisotropic Organic FET and its method of preparation 

116

200610089346.9  

A method to fabricate self alignment emitter of  InP heterojunction bipolar transistor 

117

200610089453.1  

A  System of realization of IO and interconnection of host processor and coprocessor and its method 

118

200610104114.6  

A method to measure the reverse recovery time of PIN  diode 

119

200610104116.5 

 A digital contents protection system and its method 

120

200610104117.X  

A Silicon device Structure on High breakdown voltage dielectric and its method of preparation 

121

200610104115.0  

A high gain wideband amplifier with thermal compensation 

122

200610109562.5  

A method of preparation for metal nano-crystal film 

123

200610109561.0  

A silicon-based  Single electron transistor with side-edge gate and its fabrication 

124

200610109563.X  

A SOI based plate fond Single electron transistor and its method of preparation

125

200610112107.0  

A SOI based plate fond Single electron transistor and its method of preparation 

126

200610112408.3  

A  fabrication method of heat sink for gallium arsenide monolithic microwave integrated circuit power amplifier 

127

200610112552.7  

A micro -cantilever beam sensor with triangular structure and its fabrication method 

128

200610112701.X  

A fabrication method of silicon bulk contact device on low gate extended capacitor dielectric

129

200610112884.5  

A fabrication method for non -cooling Infrared FPA detector 

130

200610112885.X  

A gallium arsenide PIN  diode and its fabrication 

8 Utility Model Patents 

 

Patent application number

Title of Utility Model

1

200420003865.5  

A large area uniform RF cold plasma generator at atmospheric pressure

2

200420004986.1  

A RF low temperature cold plasma discharge channel assembly at atmospheric pressure 

3

200520023097.4  

A equipment for improving  solid state sublimation and release in sacrifice layer

4

200420004987.6 

 A low temperature cold plasma discharge channel assembly at atmospheric pressure 

5

200420118110.X  

A nano-impression lithography tool

6

200520129718.7  

A closed loop controlled gain amplifier with comparator and digital logic as feedback loop

7

200720103995.X  

A carbon dioxide supercritical drying assembly 

8

 200720103994.5  

A carbon dioxide supercritical drying assembly with semiconductor refrigeration

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Last updated :2008-08-07 14:08:50